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AN1330 APPLICATION NOTE
DESIGNING WITH L5970D, 1A HIGH EFFICIENCY DC/DC CONVERTER
by Massimiliano Merisio
L5970D INTRODUCTION The L5970D is a step down monolithic power switching regulator capable to deliver up to 1A at output voltages from 1.235V to 35V. The operating input voltage ranges from 4.4V to 36V. It is realized in BCDV technology and the power switching element is realised by a P-Channel D-MOS transistor. It doesn't require a bootstrap capacitor, and the duty cycle can range up to 100%. An internal oscillator fixes the switching frequency at 250KHz. This minimizes the LC output filter. Synchronization pin is available in the case higher frequency (up to 500KHz) is requested. Pulse by pulse and frequency foldback overcurrent protections offer an effective short circuit protection. Other features are voltage feed forward, protection against feedback disconnection, inhibit and thermal shutdown. Figure 1. Demoboard
L5970D (SO8) Board Dimensions: 23 x 20 mm
Figure 2. Package
Figure 3. Pins connection
OUT SYNC
1 2 3 4
D98IN955
8 7 6 5
VCC GND VREF FB
SO8
INH COMP
October 2001
1/19
AN1330 APPLICATION NOTE
PINS FUNCTIONS
N. 1 2 Name OUT SYNC Regulator Output. Master/Slave Synchronization. When it is open, a signal synchronous with the turn-off of the internal power is present at the pin. When connected to an external signal at a frequency higher than the internal one, then the device is synchronized by the external signal. Connecting together the SYNC pin of two devices, the one with the higher frequency works as master and the other one, works as slave. A logical signal (active high) disables the device. With IHN higher than 2.2V the device is OFF and with INH lower than 0.8V, the device is ON. If INH is not used the pin must be grounded. When it is open, an internal pull-up disables the device. Description
3
INH
4 5
COMP E/A output to be used for frequency compensation. FB Stepdown feedback input. Connecting the output voltage directly to this pin results in an output voltage of 1.235V. An external resistor divider is required for higher output voltages (the typical value for the resistor connected between this pin and ground is 4.7K). Reference voltage of 3.3V. No filter capacitor is needed to stability. Ground. Unregulated DC input voltage.
6 7 8
VREF GND VCC
BLOCK DIAGRAM Figure 4. Block Diagram
VCC
TRIMMING
VOLTAGES MONITOR SUPPLY THERMAL SHUTDOWN
VREF BUFFER
VREF
1.235V 3.5V PEAK TO PEAK CURRENT LIMIT
INH COMP FB 1.235V SYNC
INHIBIT
E/A + + -
PWM
D
Q DRIVER FREQUENCY SHIFTER LPDMOS POWER
Ck
OSCILLATOR
GND
OUT
D00IN1125
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AN1330 APPLICATION NOTE
FUNCTIONAL DESCRIPTION The main internal blocks are shown in Fig. 4, where is reported the device block diagram. They are: s A voltage regulator that supplies the internal circuitry. From this regulator, a 3.3V reference voltage is externally available. s A voltage monitor circuit that checks the input and internal voltages. s A fully integrated sawtooth oscillator whose frequency is 250KHz 15%, including also the voltage feed forward function and an input/output synchronization pin. s Two embedded current limitations circuitries which control the current that flows through the power switch. The Pulse by Pulse Current Limit forces the power switch OFF cycle by cycle if the current reaches an internal threshold, while the Frequency Shifter reduces the switching frequency in order to strongly reduce the duty cycle. s A transconductance error amplifier. s A pulse width modulator (PWM) comparator and the relative logic circuitry necessary to drive the internal power. s An high side driver for the internal P-MOS switch. s An inhibit block for stand-by operation. s A circuit to realize the thermal protection function. POWER SUPPLY &VOLTAGE REFERENCE The internal regulator circuit (shown in Figure 5) consists of a start-up circuit, an internal voltage Preregulator, the Bandgap voltage reference and the Bias block that provides current to all the blocks. The Starter gives the start-up currents to the whole device when the input voltage goes high and the device is enabled (inhibit pin connected to ground). The Preregulator block supplies the Bandgap cell with a preregulated voltage VREG that has a very low supply voltage noise sensitivity. VOLTAGES MONITOR An internal block senses continuously the Vcc, Vref and Vbg. If the voltages go higher than their thresholds, the regulator starts to work. There is also an hysteresis on the V CC (UVLO). Figure 5. Internal Regulator Circuit
VCC
STARTER
PREREGULATOR VREG BANDGAP
IC BIAS
D00IN1126
VREF
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AN1330 APPLICATION NOTE
OSCILLATOR & SYNCHRONIZATOR Figure 6 shows the block diagram of the oscillator circuit. The Clock Generator provides the switching frequency of the device that is internally fixed at 250KHz. The frequency shifter block acts reducing the switching frequency in case of strong overcurrent or short circuit. The clock signal is then used in the internal logic circuitry and is the input of the Ramp Generator and Synchronizator blocks. The Ramp Generator circuit provides the sawtooth signal, used to realize the PWM control and the internal voltage feed forward, while the Synchronizator circuit generates the synchronization signal. Infact the device has a synchronization pin that can works both as Master and Slave. As Master to synchronize external devices to the internal switching frequency. As Slave to synchronize itself by external signal up to 500KHz. In particular, connecting together two devices, the one with the lower switching frequency works as Slave and the other one works as Master. To synchronize the device, the SYNC pin has to pass from a low level to a level higher than the synchronization threshold with a duty cycle that can vary approximately from 10% to 90%, depending also on the signal frequency and amplitude. The input can be driven directly from a TTL logic signal and the synchronization signal must be at least higher than the internal switching frequency of the device (250KHz). Figure 6. Oscillator Circuit Block Diagram
FREQUENCY SHIFTER
CLOCK
t
Ibias_osc CLOCK GENERATOR RAMP GENERATOR
RAMP
SYNCHRONIZATOR
D00IN1131
SYNC
CURRENT PROTECTION The L5970D has two current limit protections, pulse by pulse and frequency fold back. The schematic of the current limitation circuitry for the pulse by pulse protection is shown in figure 7. The output power PDMOS transistor is split in two parallel PDMOS. The smallest one has a resistor in series, RSENSE. The current is sensed through Rsense and if reaches the threshold, the mirror is unbalanced and the PDMOS is switched off until the next falling edge of the internal clock pulse. Due to this reduction of the ON time, the output voltage decreases. Since the minimum switch ON time (necessary to avoid false overcurrent signal) is not enough to obtain a sufficiently low duty cycle at 250KHz, the output current, in strong overcurrent or short circuit conditions, could increase again. For this reason the switching frequency is also reduced, so keeping the inductor current under its maximum threshold. The Frequency Shifter (see fig. 6) depends on the feedback voltage. As the feedback voltage decreases (due to the reduced duty cycle), the switching frequency decreases too.
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AN1330 APPLICATION NOTE
Figure 7. Current Limitation Circuitry
VCC IOFF DRIVER A1 A2 IL RSENSE RTH
OUT A1/A2=95 I PWM
D00IN1134
I
NOT
ERROR AMPLIFIER The voltage error amplifier is the core of the loop regulation. It is a transconductance operational amplifier whose non inverting input is connected to the internal voltage reference (1.235V), while the inverting input (FB) is connected to the external divider or directly to the output voltage. The output (COMP) is connected to the external compensation network. The uncompensated error amplifier has the following characteristics:
Transconductance Low frequency gain Minimum sink/source voltage Output voltage swing Input bias current 2300S 65dB 1500A/300A 0.4V/3.65V 2.5A
The error amplifier output is compared with the oscillator sawtooth to perform PWM control. PWM COMPARATOR AND POWER STAGE This block compares the oscillator sawtooth and the error amplifier output signals generating the PWM signal for the driving stage. The power stage is a very critical block cause it has to guarantee a correct turn on and turn off of the PDMOS. The turn on of the power element, or better, the rise time of the current at turn on, is a very critical parameter to compromise. At a first approach, it looks like the faster it is the rise time, the lower are the turn on losses. But there is a limit introduced by the recovery time of the recirculation diode. In fact when the current of the power element equals the inductor current, the diode turns off and the drain of the power is free to go high. But during its recovery time, the diode can be considered as an high value capacitor and this produces a very high peak current, responsible of many problems: s Spikes on the device supply voltage that cause oscillations (and thus noise) due to the board parasitics. s Turn on overcurrent causing a decrease of the efficiency and system reliability. s Big EMI problems. s Shorter freewheeling diode life. The fall time of the current during the turn off is also critical. In fact it produces voltage spikes (due to the parasitics elements of the board) that increase the voltage drop across the PDMOS.
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AN1330 APPLICATION NOTE
In order to minimize all these problems, a new topology of driving circuit has been used and its block diagram is shown in fig. 8. The basic idea is to change the current levels used to turn on and off the power switch, according with the PDMOS status and with the gate clamp status. This circuitry allow to turn off and on quickly the power switch and to manage the above question related to the freewheeling diode recovery time problem. The gate clamp is necessary to avoid that Vgs of the internal switch goes higher than Vgsmax. The ON/OFF Control block avoids any cross conduction between the supply line and ground. Figure 8. Driving Circuitry
VCC
Vgsmax IOFF CLAMP GATE
PDMOS DRAIN VOUT L ESR ILOAD
STOP DRIVE DRAIN ON/OFF CONTROL
OFF
ON C ION
D00IN1133
INHIBIT FUNCTION The inhibit feature allows to put in stand-by mode the device. With INH pin higher than 2.2V the device is disabled and the power consumption is reduced to less than 100A. With INH pin lower than 0.8V, the device is enabled. If the INH pin is left floating, an internal pull up ensures that the voltage at the pin reaches the inhibit threshold and the device is disabled. The pin is also Vcc compatible. THERMAL SHUTDOWN The shutdown block generates a signal that turns off the power stage if the temperature of the chip goes higher than a fixed internal threshold (150C). The sensing element of the chip is very close to the PDMOS area, so ensuring an accurate and fast temperature detection. An hysteresis of approximately 20C avoids that the devices turns on and off continuously ADDITIONAL FEATURES AND PROTECTIONS FEEDBACK DISCONNECTION In case of feedback disconnection, the duty cycle increases versus the maximum allowed value, bringing the output voltage close to the input supply. This condition could destroy the load. To avoid this dangerous condition, the device is turned off if the feedback pin remains floating.
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AN1330 APPLICATION NOTE
OUTPUT OVERVOLTAGE PROTECTION The overvoltage protection, OVP, is realized by using an internal comparator, which input is connected to the feedback, that turns off the power stage when the OVP threshold is reached. This threshold is typically 30% higher than the feedback voltage. When a voltage divider is requested for adjusting the output voltage (see figure 14), the OVP intervention will be set at: R1 + R2 V O VP = 1.3 -------------------- V FB R2 Where R1 is the resistor connected between the output voltage and the feedback pin, while R2 is between the feedback pin and ground. ZERO LOAD Due to the fact that the internal power is a PDMOS, no boostrap capacitor is required and so, the device works properly also with no load at the output. In this condition it works in burst mode, with random repetition rate of the burst. CLOSING THE LOOP Compensation Network The output L-C filter of a step down converter contributes with 180 degrees phase shift in the control loop. For this reason a compensation network between the COMP pin and ground is added. The simplest loop compensation network is shown in fig. 9. RC and CC introduce a pole and a zero in the open loop gain. CP doesn't affect really the system stability but is useful to reduce the noise of the COMP pin. Figure 9. Compensation Network
+ FB E/A COMP RC CC
D00IN1129A
CP
The equivalent circuit of the error amplifier is shown in fig.10 Figure 10. Error Amplifier Equivalent Circuit
V+ V Gm*V RO 0.8M
D00IN1308
CO 220pF
Considering RC = 2.7k, CC = 22nF and CP = 220pF (see fig. 14), the transfer function Ao(s) of the error amplifier and its compensation network becomes: A vo ( 1 + s R c C c ) A o ( s ) = -----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------2 s R o ( Co + C p ) Rc Cc + s ( R o C c + Ro ( C o + C p ) + Rc C c ) + 1 Where Avo = Gm * Ro
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AN1330 APPLICATION NOTE
The poles and zeroes of this transfer function are: 1 1 F P1 = --------------------------------- = ---------------------------------------------------------------------- = 9H z -9 6 2 R o Cc 2 [ 0.8 10 ] 22 10 1 1 F P2 = ---------------------------------------------------- = ------------------------------------------------------------------- = 134kH z - 12 3 2 Rc ( C o + C p ) 2 2.7 10 220 10 1 1 F Z 1 = --------------------------------- = ------------------------------------------------------------- = 2.673kHz -9 3 2 Rc C c 2 2.7 10 22 10 Fp1 is the low frequency pole that sets the bandwidth while the zero Fz1 is usually put near to the frequency of the double pole of the L-C filter (see below). Fp2 is usually at a very high frequency. The transfer function of the L-C filter is given by: 1 + ESR C OUT s A L C ( s ) = ----------------------------------------------------------------------2 L C OUT s + ESR S + 1 The poles and zeroes of this transfer function are: 1 1 F PL C = ------------------------------------------ = --------------------------------------------------------------------- = 3.393kHz -6 -6 2 L C OUT 22 10 100 10 2 1 1 F o = ------------------------------------------------ = ----------------------------------------------------- = 19.89kHz -6 2 ESR C OUT 2 0.08 100 10 Fo is the zero introduced by the ESR of the output capacitor and it is very important to increase the phase margin of the control loop. FpLC is the double pole of the L-C filter. The PWM gain is given by the following formula: V cc G PW M ( s ) = -------------------------------------------------------------( V OS CMAX - V OSCM IN ) Where VOSCMAX is the maximum value of a sawtooth waveform and VOSCMIN is the minimum one. A voltage feed forward is realized to have GPWM constant. This feature is obtained generating a sawtooth waveform directly proportional to the input voltage VCC. VOSCMAX - VOSCMIN = K * VCC Where K is equal to 0.076. Therefore the PWM gain is also equal to 1 G PW M ( s ) = --- = Co nst K This means that also if the input voltage changes, the error amplifier doesn't change its value to keep the loop in regulation, so ensuring a better line regulation and line transient response. To sumup the Open Loop Gain can be written as: R2 G ( s ) = G PW M ( s ) -------------------- A o ( s ) A L C ( s ) R1 + R 2 The Gain and Phase Bode are plotted in figures 11 and 12.
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AN1330 APPLICATION NOTE
Figure 11. Module Plot
90 80 70 60 Module (dB) 50 40 30 20 10 0 10 0.1 1 10 100 1 .10 Frequency [Hz]
3
1 .10
4
1 .10
5
1 .10
6
Figure 12. Phase Plot
0
40
Phase
80
120
160
200 0.1
1
10
100 1 .10 Frequency [Hz]
3
1 .10
4
1 .10
5
1 .10
6
The cut off frequency and the phase margin are: FC = 22.8KHz Phase Margin = 35
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AN1330 APPLICATION NOTE
APPLICATION INFORMATIONS COMPONENTS SELECTION Input capacitor The input capacitor must be able to support the maximum input operating voltage and the maximum RMS input current. Since step-down converters draw current from the input in pulses, the input current is squared and the height of each pulse is equal to the output current. The input capacitor has to absorb all this switching current that can be up to the load current divided by two (worst case, with duty cycle of 50%). For this reason, the quality of these capacitors has to be very high to minimize its power dissipation generated by the internal ESR, so improving the system reliability and efficiency. The critical parameter is usually the RMS current rating that has to be higher than the RMS input current. The maximum RMS input current (flowing through the input capacitor) is: D 2D I RM S = I O D - -------------- + -----
2 2
Where is the expected system efficiency, D is the duty cycle and Io the output DC current. This function reaches its maximum value at D = 0.5 and the equivalent RMS current is equal to IO divided by 2 (considering = 1). The maximum and minimum duty cycles are: V OUT + V F D MAX = ------------------------------------V INM IN - V S W and V OUT + V F D M IN = -------------------------------------V INMAX - V SW
Where VF is the freewheeling diode forward voltage and VSW the voltage drop across the internal PDMOS. Considering the range DMIN to DMAX it is possible to determine the max IRMS following through the input capacitor. Different capacitors can be considered: - Electrolytic Capacitors. These are the most used cause are the cheapest ones and are available with a wide range of RMS current ratings. The only drawback is that, considering a requested ripple current rating, they are physically larger than other capacitors. - Ceramic Capacitors. If available for the requested value and voltage rating, these capacitors have usually an higher RMS current rating for a given physical dimension (due to the very low ESR). The drawback is the quite high cost. - Tantalum Capacitor. Very good tantalum capacitors are coming available, with very low ESR and small size. The only problem is that they occasionally can burn if subjected to very high current during the charge. So, it is better avoid this type of capacitors for the input filter of the device. Infact, they can be subjected to high surge current when connected to the power supply. Output capacitor The output capacitor is very important to satisfy the output voltage ripple requirement. Using a small inductor value is useful to reduce the size of the choke but increases the current ripple. So, to reduce the output voltage ripple a low ESR capacitor is required. Nevertheless, the ESR of the output capacitor
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AN1330 APPLICATION NOTE
introduces a zero in the open loop gain, that helps to increase the phase margin of the system. If the zero goes at very high frequency, its effect is negligible. For this reason, ceramic capacitors and very low ESR capacitors in general should be avoided. Tantalum and electrolytic capacitors are usually good for this use. Below there is a list of some tantalum capacitors manufacturer. Table 1.
Manufacturer AVX KEMET SANYO POSCAP(*) SPRAGUE TPS T494/5 TPA/B/C 595D Series Cap Value (F) 100 to 470 100 to 470 100 to 470 220 to 390 Rated Voltage (V) 4 to 35 4 to 20 4 to 16 4 to 20 ESR (m) 50 to 200 30 to 200 40 to 80 160 to 650
(*) POSCAP capacitors have characteristic very similar to tantalum ones.
Inductor The inductor value is very important cause it fixes the ripple current flowing through output capacitor. The ripple current is usually fixed at 20-40% of Iomax, that is 0.2-0.4A with Iomax = 1A. The inductor value is approximately obtained by the following formula: ( V IN - V OUT ) L = ---------------------------------- T O N I where Ton is the ON time of the internal switch, given by D * T. For example, with VOUT = 3.3V, VIN = 12V and IO = 0.3A, the inductor value is about 35H. The peak current thought the inductor is given by: I I PK = I O + ---2 and it can be seen that if the inductor value decreases, the peak current (that has to be lower than the current limit of the device) increases. So, fixed the peak current, higher value of the inductor permit higher value for the output current. In the following table some inductor manufacturer are listed. Table 2.
Manufacturer Coilcraft Series DO1813HC DO3316 Coiltronics UP1B UP2B BI HM76-2 HM76-3 Murata PANASONIC SUMIDA LQN6C ELLATV CR75 Inductor Value (H) 22 to 33 33 to 47 22 to 33 33 to 47 22 to 33 33 to 47 22 to 33 22 to 47 22 to 33 Saturation Current (A) 1 to 1.2 1.6 to 2 1 to 1.2 1.7 to 2 1 to 1.2 2 to 2.5 0.9 to 1.2 1.4 to 2.05 1.05 to 1.25
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AN1330 APPLICATION NOTE
LAYOUT CONSIDERATIONS The layout of switching DC/DC converters is very important to minimize noise and interference. Power-generating portions of the layout are the main cause of noise and so high switching current loop areas should be kept as small as possible and lead lengths as short as possible. High impedance paths (in particular the feedback connections) are susceptible to interference and so they should be as far as possible from the high current paths. Below there is a layout example (Fig. 13). The input and output loops are minimized to avoid radiation and high frequency resonance problems. The feedback pin connections to the external divider are very close to the device to avoid pick up noise. Moreover the GND pin of the device is connected to the ground plane directly with VIA on the bottom side of the PCB. Figure 13. Layout example
COMPENSATION NETWORK FAR FROM HIGH CURRENT PATHS
to output voltage
MINIMUN SIZE OF FEEDBACK PIN CONNECTIONS TO AVOID PICKUP
Inhibit signal
R2 5 R1 8 L5970 1 Vout Cin D Cout Gnd 4 L
CONNECTION TO GROUNDPLANE THROUGH VIA
Vin
VERY SMALL HIGH CURRENT CIRCULATING PATH TO MINIMIZE RADIATION AND HIGH FREQUENCY RESONANCE PROBLEMS
OUTPUT CAPACITOR DIRECTLY CONNECTED TO HEAVY GROUND
THERMAL CONSIDERATIONS The dissipated power of the device is related to three different sources: - switch losses due to the not negligible RDSON. These are equal to: P O N = R DSON ( I OUT ) D Where D is the duty cycle of the application. Note that the duty cycle is theoretically given by the ratio between Vout and Vin, but in practical is quite higher than this value to compensate the losses of the overall application. Due to this reason, the switch losses related to the RDSON increases compared with the ideal case. - Switch losses due to its Turn On and Off. These are given by the following relation: ( T O N + T O FF ) P SW = V IN I OUT ------------------------------------ F SW = V IN I OUT T S W F SW 2 Where TON and TOFF are the overlap times of the voltage across the power switch and the current flowing into
12/19
2
AN1330 APPLICATION NOTE
it during the Turn On and Turn Off phases. TSW is the equivalent switching time. - Quiescent current losses. P Q = V IN I Q Where IQ is the quiescent current. Example: Vin = 5V Vout = 3.3V Iout = 1A RDSON has a typical value of 0.25 @ 25C and increases up to a maximum value of 0.5 @ 150C. We can consider a value of 0.4. TSW is approximately 120ns. IQ has a typical value of 2.5mA @ Vin = 12V. The overall losses are:
P T OT = R DSON ( I OUT ) D + V IN I OUT T SW F SW + V IN I Q = = 0.4 1 0.7 + 5 1 120 10 The junction temperature of device will be: TJ = TA + RthJ-A * PTOT Where TA is the ambient temperature and RthJ-A is the thermal resistance junction to ambient. Considering that the device in SO8 package mounted on board with a good groundplane has a thermal resistance junction to ambient (Rth J-A) of about 115C/W and considering an ambient temperature of about 70C TJ = 70 + 0.44 * 115 121C
2 -9
2
250 10 + 5 2.5 10
3
-3
0.44W
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AN1330 APPLICATION NOTE
APPLICATION CIRCUIT In figure 14 is shown the demo board application circuit for the device in SMD version, where the input supply voltage, Vcc, can range from 4.4V to 25V due to the rated voltage of the input capacitor and the output voltage is adjustable from 1.235V to V cc. Figure 14. Demo board Application Circuit
VINmax=25V
VCC
OUT
L1 22uH Coilcraft
D1 STPS2L25U
VOUT=3.3V
8 U1 L5970D 4 2
C4 220pF C3 22nF R3 2.7k SYNC VREF
1
FB R1 5.6k C2 Sanyo Poscap 100uF 10V
COMP C1 10uF 25V TOKIN
6
GND
7
5 3
INH
R2 3.3k
3.3V
Table 3. Component List
Reference C1 C2 C3 C4 R1 R2 R3 D1 L1 STPS2L25U DO3316P-333 10TPB100M C1206C223K5RAC C1206C221J5GAC Part Number Description 10F, 25V 100F, 10V 22nF, 10%, 50V 220pF, 5%, 50V 5.6K, 1%, 0.25W 3.3K, 1%, 0.25W 2.7K, 1%, 0.25W 2A, 25V 22H, 1.2A Manufacturer TOKIN Sanyo, POSCAP KEMET KEMET Neohm Neohm Neohm ST COILCRAFT
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AN1330 APPLICATION NOTE
Figure 15. PCB layout (component side)
42mm
34mm
Figure 16. PCB layout (bottom side)
Figure 17. PCB layout (front side)
Below some graphs show the Tj versus output current in different conditions of the input and output voltage and some efficiency measurements.
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AN1330 APPLICATION NOTE
Figure 18. Junction Temperature vs. Output Current (SO8) *)
Tj(C)
Figure 21. Efficiency vs. Output Current
95 93 91 89 87 85 83 81 79 77 75
Vcc=5V
130 120 110 100 90 80 70 60 50 40 30 20 0.2
Vo=3.3V Vo=2.5V
Vo=2.5V
Vcc=5V Tamb=25C
Vo=1.8V
Efficiency(%)
Vo=3.3V
Vo=1.8V
0.1 0.2 0.3
0.4 0.6 0.8
Io(A)
0.4
0.5 0.6 0.7 0.8 0.9 Io(A)
1
1
1.2
1.4
1.6
Figure 22. Efficiency vs. Output Current Figure 19. Junction Temperature vs. Output Current (SO8) *)
Tj(C)
90 88 86 84
Efficiency(%)
Vo=5V
130 120 110 100 90 80 70 60 50 40 30 20 0.2
Vo=5V
Vo=3.3V
Vcc=12V Tamb=25C
Vo=2.5V
82 80 78 76 74 72 70
Vcc=12V
Vo=3.3V Vo=2.5V
0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9
Io(A)
1
0.4
0.6
0.8
Io(A)
1
1.2
1.4
1.6
Figure 20. Junction Temperature vs. Output Current (SO8) *)
Tj(C)
140
Vo=18V
Vo=12V
120 100 80 60 40 20 0 0.2 0.4 0.6 0.8
Io(A) Vcc=24V Tamb=25C Vo=5V
1
1.2
1.4
*) Package mounted on demoboard
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AN1330 APPLICATION NOTE
APPLICATION IDEAS POSITIVE BUCK-BOOST REGULATOR The device can be used to realize an Up-Down converter with a positive output voltage. In figure is shown the schematic circuit of this topology for an output voltage of 12V. The input voltage can range from 5V and 35V. The output voltage is given by Vo=Vin * D/(1-D), where D is duty cycle. The maximum output current is given by Iout=1x (1-D). The current capability is reduced by the term (1-D) and so, for example, with a duty cycle of 0.5, the maximum output current deliverable to the load is 0.5A. This is due to the fact that the current flowing trough the internal power switch is delivered to the output only during the OFF phase. Figure 23. Positive Buck-Boost regulator
L1 33uH
D2 STPS2L25U
VIN=5V - 35V
VCC
OUT
VOUT=12V/0.3A
8 U1 L5970D 4 2 6
VREF GND
1
D1 STPS2L25U R1 5.6k M1 STN4NE03L R2 3.3k C4 100uF 16V
COMP C1 10uF 35V Ceramic
7
5 3
FB
C2 220pF
C3 22nF R3 4.7k
SYNC
INH
3.3V
Vin = 5V Vout = 12V
Iout = 0.3A
Efficiency = 76%
BUCK-BOOST REGULATOR In Figure 24 is shown the schematic circuit to realize a standard Buck-Boost topology. The output voltage is given by Vo=-Vin * D/(1-D). The maximum output current is equal to Iout=1 * (1-D), for the same reason of the Up-Down converter. An important thing to take in account is that the Gnd pin of the device is connected to the negative output voltage. So, the device undergoes a voltage equal to Vin-Vo, that has to be lower than 36V (maximum operating input voltage). Figure 24. Buck-Boost regulator
L1 33uH
VIN=12V
VCC
OUT
8 U1
COMP C1 10uF 25V Ceramic C2 10uF C3 35V Ceramic 220pF
1
R1 5.6k D1 STPS2L25U VOUT=-12V/0.3A
L5970D 4 2 6
GND
7
5 3
FB
C4 22nF R3 4.7k
SYNC VREF
INH
R2 3.3k
C5 100uF 16V
3.3V
Vin = 12V Vout = -12V
Iout = 0.5A
Efficiency = 81%
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AN1330 APPLICATION NOTE
DUAL OUTPUT VOLTAGE WITH AUXILIARY WINDING When two output voltages are required, it is possible to realize a dual output voltage converter by using a coupled inductor. During the ON phase the current is delivered to Vout while D2 is reverse biased. During the OFF phase the current is delivered, through the auxiliary winding, to the output voltage Vout1. This is possible only if the magnetic core has stored a sufficient energy. So, to be sure that the application is working properly, the load related to the second output Vout1 should be much lower than the load related to Vout. Figure 25. Dual output voltage with auxiliary winding
N1/N2=2 D2 1N4148 VOUT1=5V 30mA
VIN=12V
VCC
8
COMP C1 10uF 25V Ceramic
OUT
Lp=22uH D1 STPS25L25U VOUT=3.3V 0.5A C4 100uF 10V C5 47uF 10V
1 U1 L5970D
FB
4 2 6
GND
7
5 3
C2 220pF
C3 22nF R3 4.7k
SYNC VREF
INH
3.3V
SYNCHRONIZATION EXAMPLE Two or more devices (up to 6) can be synchronized just connecting together the synchronization pin. In this case, the device with an slightly higher switching frequency value will work as master and the ones with a slightly lower switching frequency value will work as a slave. The device can also be synchronized from an external source. In this case the logic signal (see synchronization section) must have a frequency higher than the internal switching frequency of the device (250KHz). Figure 26. Synchronization example
VIN VCC OUT VCC OUT
8 L5970D 4 2
SYNC VREF
1
FB COMP
8 L5970D 4 2
SYNC VREF
1
FB
COMP
6
GND
7
5 3
6
GND
7
5 3
INH
INH
18/19
AN1330 APPLICATION NOTE
Information furnished is believed to be accurate and reliable. However, STMicroelectronics assumes no responsibility for the consequences of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of STMicroelectronics. Specifications mentioned in this publication are subject to change without notice. This publication supersedes and replaces all information previously supplied. STMicroelectronics products are not authorized for use as critical components in life support devices or systems without express written approval of STMicroelectronics. The ST logo is a registered trademark of STMicroelectronics (R) 2001 STMicroelectronics - All Rights Reserved STMicroelectronics GROUP OF COMPANIES Australia - Brazil - China - Finland - France - Germany - Hong Kong - India - Italy - Japan - Malaysia - Malta - Morocco - Singapore - Spain - Sweden - Switzerland - United Kingdom - U.S.A. http://www.st.com
19/19

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